Blind and buried vias solve one specific problem: they let you route high-density PCBs without punching holes through layers you don't need to connect. Blind vias run from a surface layer partway into the stack; buried vias stay completely inside, connecting only internal layers. Both cost more than through-holes and demand tighter process control, but when you're fanning out a 0.4 mm pitch BGA or stacking eight signal layers under a processor, they're often the only option that works.
Key Takeaways
- Blind vias preserve the opposite surface for routing; buried vias free both outer layers but lock you into sequential lamination.
- Laser microvias (75–150 µm) support HDI fanout, but copper thickness in small diameters is the failure point I see most often.
- Buried vias must be planned in the initial stackup—adding them after layout starts usually means scrapping cores already in production.
- Through-via stubs hurt signal integrity above 10 GHz; blind vias cut stub length, buried vias eliminate it entirely within their layer span.
- Cost scales with the number of lamination cycles, not via count—one buried-via pair is manageable, three pairs doubles your NRE and lead time.
Why Blind Vias Exist
A blind via connects an outer copper layer to one or more internal layers without breaking through to the opposite side. You drill or laser it after lamination, control the depth to hit a specific capture pad, then plate it. The result: surface components get access to inner-layer routing while the back side stays intact.
In practice, blind vias are most useful when you need to escape a dense BGA or QFN without stealing routing channels from the bottom layer. The tradeoff is depth control—over-drill by 50 µm and you short to the wrong plane; under-drill and your plating doesn't reach the pad. I've seen boards fail incoming inspection because the fab's depth calibration drifted between panel runs.
Mechanical blind vias typically range from 200 to 300 µm in diameter and can span two or three layers if the aspect ratio stays under 1:1. Laser-drilled microvias are much smaller—75 to 150 µm—but they're limited to one dielectric layer per shot, usually around 60–120 µm deep. If you need to go deeper, you stack microvias with staggered or vertically aligned landing pads, which adds another lamination cycle and another place for misregistration to creep in.
What Buried Vias Actually Do
Buried vias live entirely inside the PCB. They connect internal layer pairs and never reach the surface, so both top and bottom layers remain available for components and traces. You form them by drilling the inner cores before outer-layer lamination, plating the holes, then pressing the whole stack together. Once laminated, they're permanent—there's no access for inspection or rework.
The main reason to use buried vias is to preserve outer-layer real estate when internal routing is dense but surface space is at a premium. According to my experience on controller boards with 10+ layers, buried vias also shorten signal paths between inner planes, which helps when you're trying to match trace lengths on a DDR4 or PCIe interface.
The catch: you must define every buried-via layer pair before the first core goes to imaging. If you discover during layout that you need a buried connection you didn't plan for, your options are to re-spin the stackup (expensive, slow) or find a workaround with through-vias or blind vias (which may not fit). This is why I always map out power distribution and critical signal layers in the stackup spreadsheet before routing starts, even when it feels premature.
Buried vias are typically 250–400 µm in diameter, drilled mechanically on the inner cores. Aspect ratio limits still apply, but because you're working with thinner core pairs, you can often hit tighter geometries than you'd get drilling the full board thickness.
Blind vs. Buried: When to Use Which
| Comparison Point | Blind Vias | Buried Vias |
|---|---|---|
| Connections | Outer layer to one or more inner layers | Inner layer to inner layer only |
| Outer-layer impact | Consumes pad space on one surface | Leaves both surfaces fully available |
| Typical depth | 1–3 layers (~100–400 µm) | Fixed by core thickness and layer pair selection |
| Fabrication timing | Drilled after partial or full lamination | Drilled on inner cores before outer lamination |
| Diameter range | 75–300 µm (laser or mechanical) | 250–400 µm (mechanical) |
| Inspection access | One surface visible | Fully enclosed, X-ray or cross-section only |
| Flexibility | Can be added mid-design if stackup permits | Must be locked in during stackup definition |
| Cost driver | Controlled-depth drilling and selective plating | Additional lamination cycles and alignment |
Use blind vias when surface routing is constrained and you need to escape high-pin-count parts without consuming the opposite layer. Use buried vias when both outer layers are full and internal signal routing justifies the added process complexity. Don't use either if through-vias will work—every non-standard via type increases your fabrication cost, lead time, and rejection risk.
How These Vias Are Actually Built
Manufacturing blind and buried vias requires sequential build-up, meaning the board is laminated in stages rather than all at once. Buried vias are drilled and plated on individual core pairs, then those cores are stacked with prepreg and laminated under heat and pressure. Blind vias are drilled after lamination, either with a mechanical drill set to a precise depth or a CO₂ or UV laser that ablates through one dielectric layer at a time.
Laser drilling is the standard method for microvias in HDI boards. A focused laser beam vaporizes the resin and glass, stopping when it hits the copper capture pad. Dwell time, power, and focus depth are all tightly controlled—if any parameter drifts, you either don't clear the dielectric or you blow through the pad. After drilling, the via is cleaned, then electroless copper is deposited to seed the barrel, followed by electrolytic plating to build up the full thickness.
Controlled-depth mechanical drilling is used for larger blind vias that span multiple layers. The drill bit is programmed to stop at a specific Z-depth, which is calculated from the stackup and confirmed with test coupons. Depth variation across a panel is usually within ±25 µm if the equipment is well-calibrated, but I've debugged failures where spindle wear or tool deflection pushed that tolerance past ±50 µm, causing intermittent pad contact.
Via filling improves reliability and enables stacked microvias by planarizing the surface. Conductive fill (copper paste or plated copper) provides a solid thermal and electrical path. Non-conductive fill (epoxy resin) is cheaper and sufficient when the via is only carrying signals. Both types require an additional process step and add cost.
Where Blind and Buried Vias Show Up
These via types appear most often in designs where density, signal speed, or layer count make traditional routing impractical:
HDI assemblies with fine-pitch BGAs: When you're fanning out a 0.4 mm or 0.5 mm pitch BGA, you don't have room for through-via pads between the balls. Microvias give you a one-layer escape path directly under the package, and you can stack them if needed to reach deeper layers.
High-speed digital boards: Processors, FPGAs, and SerDes interfaces above 10 Gbps are sensitive to via stubs. A through-via that passes unused layers creates a resonant stub that distorts the signal. Blind vias reduce stub length; buried vias eliminate the stub entirely within their layer span.
RF and mixed-signal layouts: Compact RF boards benefit from shorter vertical transitions and the ability to isolate sensitive analog layers from noisy digital ground planes. Buried vias let you route RF traces on inner layers without exposing them to surface interference.
Automotive ECUs and ADAS modules: These boards pack multiple power domains, CAN/LIN interfaces, and high-speed camera or radar links into a small footprint, often with 8–12 layers. Buried vias keep power distribution clean on inner layers, while blind vias handle dense component fanout on the surface.
Compact consumer devices: Smartphones, wearables, and other space-constrained products use HDI stackups with multiple microvia layers (sometimes called 1+N+1 or 2+N+2 builds) to maximize routing density and minimize board thickness.
Real-World Tradeoffs You Need to Know
Blind and buried vias solve routing problems, but they're not without downsides. Here's what actually goes wrong:
Small diameters mean thin copper: A 100 µm microvia might have only 15–20 µm of plated copper on the barrel after processing. If there's any voiding or roughness in the plating, current density spikes and the via can fail under thermal cycling. I've seen this happen on power pins where the design assumed the via could carry 0.5 A continuously—it couldn't.
You can't inspect what you can't see: Buried vias are locked inside the board. If one fails to plate or gets contaminated during lamination, you won't know until electrical test or—worse—after assembly. X-ray can catch gross defects, but it won't show a marginal plating thickness that fails after a few hundred thermal cycles.
Fabricators charge by lamination cycles, not via count: Adding one buried-via layer pair to your stackup means at least one additional lamination step, which typically adds 30–50% to your bare board cost and extends lead time by a week or more. If you need three buried-via pairs, expect costs to double and lead times to stretch past six weeks for prototype quantities.
Late changes are expensive: If you add blind or buried vias after the stackup is locked, the fab has to re-image inner layers, re-drill cores, and potentially scrap work in progress. I've been on projects where a single buried-via addition in layout triggered a $15K NRE charge and pushed delivery by three weeks.
Aspect ratio limits are real: Most fabs cap mechanical blind vias at 1:1 aspect ratio (depth equal to diameter), and some won't go past 0.8:1 for reliability reasons. Laser microvias are even more constrained—one layer per pass is standard, and stacking more than two or three layers vertically starts to affect yield.
When Standard Through-Vias Are Still the Right Answer
Not every dense board needs blind or buried vias. If your layer count is six or fewer, your pitch is 0.5 mm or larger, and your signals stay below 5 GHz, through-vias will almost always be simpler, cheaper, and more reliable. Back-drilling can remove most of the stub length on high-speed nets when needed, and it's a one-step process that doesn't require sequential lamination.
I also see designers spec HDI stackups with microvias when the actual routing density doesn't justify it. If you can fan out your BGA with standard vias by adding one more signal layer, that's usually the better tradeoff—cheaper, faster, and easier to rework if something goes wrong.
What's Changing in Via Technology
Via structures continue to shrink as component pitches tighten and signal speeds increase:
Smaller diameters are becoming standard: 75 µm microvias were considered aggressive five years ago; today they're routine in smartphone and wearable designs, and some fabs are piloting 50 µm capabilities for next-generation HDI.
Filled-via processes are more consistent: Conductive and non-conductive fill chemistries have improved, reducing voids and improving planarization quality, which makes stacked and staggered microvia structures more reliable.
Design tools are catching up: Modern DFM engines now flag blind-via depth violations, stacking limits, and lamination dependencies during layout rather than at Gerber review, which cuts costly late-stage changes.
Low-loss laminates handle higher frequencies: New resin systems with lower Dk and Df are allowing blind and buried vias to operate reliably at 28 GHz and beyond, which matters for 5G, 100G Ethernet, and PCIe Gen 5/6 applications.
Additive and semi-additive processes are entering production: A few high-end fabs are using modified SAP (semi-additive process) methods to build finer geometries and more controlled via structures, though this remains niche and expensive.
Final Thoughts
Blind and buried vias are tools for solving specific routing problems—not features to add because they sound advanced. Use them when through-vias won't fit, when signal integrity requires shorter stubs, or when outer-layer congestion justifies the cost. Plan them into your stackup from the start, budget for longer lead times and higher NRE, and make sure your fabricator has demonstrated capability with your chosen via types and aspect ratios before you commit the design.
The real challenge isn't knowing what these vias do—it's knowing when the added complexity is worth it and when a simpler stackup will work just as well.
