A buck converter steps down voltage via duty cycle D, but real designs collide with three constraints: inductor ripple scales inversely with frequency (ΔI = (Vin−Vout)×D/(L×fsw)), CCM-to-DCM boundary crossings cause voltage spikes, and PCB return-path inductance triggers subharmonic oscillation. Most tutorials stop at Vout=D×Vin; production boards fail when feedback loop compensation lags or layout parasitics resonate the output filter.
Key Takeaways
• Ripple-frequency coupling: Doubling switching frequency halves inductor size for same ripple, but dead-time losses rise from 0.2% at 500 kHz to 1% at 1 MHz—no free lunch • CCM-to-DCM boundary: Load dropping below I_load,min = (Vin−Vout)×D×(1−D)/(2×L×fsw) causes 400 mV output spikes if feedback loop can't track the sudden impedance change • Feedback loop bandwidth tradeoff: Voltage-mode control has phase lag limiting bandwidth to 50–100 kHz; current-mode pushes to 200–300 kHz but creates subharmonic oscillation risk above D=0.5 without slope compensation • Dead-time efficiency loss: 10 ns dead-time at 1 MHz switching costs 1% efficiency; same dead-time at 500 kHz costs 0.2%—architecture choice sets floor • PCB layout as instability source: Return-path inductance above 100 nH couples with output filter capacitance, creating 10 MHz resonance that voltage feedback can't correct—oscilloscope shows 200 mV spikes at switching node even with "stable" output
Output Voltage Formula and Real Constraints
The ideal equation Vout = D × Vin holds only in steady state with zero losses. In practice, three corrections apply:
- Conduction losses: MOSFET Rds(on) and inductor DCR drop 2–5% of output voltage under load
- Transient overshoot: Load steps cause 10–15% voltage excursions until feedback loop responds (100–300 µs typical)
- Input voltage rejection: Ripple from input supply appears at output, attenuated by 20–40 dB depending on feedback crossover frequency
Duty cycle adjusts dynamically to compensate for these losses. A 12V-to-5V design needs D ≈ 0.42 ideally, but real converters run D = 0.45–0.48 to offset resistive drops.
Inductor Behavior and Ripple Current
Inductor current rises during switch ON-time and falls during OFF-time, creating triangular ripple around the average load current. The ripple amplitude follows:
ΔI = (Vin − Vout) × D / (L × fsw)
This equation reveals the core design tradeoff: higher switching frequency allows smaller inductors for the same ripple percentage, but increases switching losses and dead-time inefficiency. From my observation of production designs, 500 kHz switching with 10 µH inductors dominates cost-sensitive applications, while 1 MHz with 4.7 µH serves space-constrained layouts willing to accept 2–3% efficiency penalty.
The folklore "ripple should be 20–40% of load current" lacks physics justification. Ripple percentage affects inductor size and output capacitor ESR requirements, but optimal ripple depends on application: low-noise analog supplies target 10–15%, high-current CPU converters tolerate 30–50% to minimize inductor cost.
Conduction Modes: CCM and DCM Boundary
Continuous Conduction Mode (CCM) keeps inductor current always positive. Discontinuous Conduction Mode (DCM) allows current to hit zero before the next cycle. The boundary occurs at:
I_load,min = (Vin − Vout) × D × (1 − D) / (2 × L × fsw)
Crossing this boundary during operation creates a control problem. In CCM, the converter acts as a voltage source with predictable output impedance. In DCM, output impedance jumps, and if feedback loop bandwidth is too narrow to track the transition, output voltage spikes 200–400 mV until regulation catches up.
I've debugged designs where light-load efficiency optimization forced DCM operation, but the product specification required tight voltage regulation across all loads. The fix required hybrid control: CCM at rated load with inductor sized for 30% ripple, then accepting DCM below 20% load with feed-forward compensation to predict the impedance jump. Bigger inductor would have kept CCM down to 5% load, but cost and size constraints ruled it out.
Control Methods and Feedback Loop Compensation
Four common control architectures exist, each with different stability challenges:
Voltage-mode control measures output voltage and adjusts duty cycle. Simple, but the inductor-capacitor output filter creates a double pole at resonant frequency, causing 180° phase lag. Crossover frequency must stay below fs/10 to maintain stability, limiting bandwidth to 50–100 kHz for typical 500 kHz–1 MHz switching frequencies. Load transient response suffers.
Current-mode control measures inductor current each cycle, converting the inductor into a controlled current source and removing one pole from the loop. This pushes achievable bandwidth to 200–300 kHz. The cost: above D=0.5, the system develops subharmonic oscillation from the inductor current ramp. Slope compensation (adding an artificial ramp to the PWM comparator) fixes this, but the compensation must track across temperature and input voltage, or instability returns.
Constant-On-Time (COT) fixes the switch ON-time and varies frequency to regulate output. Very fast transient response (sub-microsecond) and no compensation components. The limitation: requires output capacitors with enough ESR to create a ripple voltage that the comparator can measure. Ceramic capacitors with ultra-low ESR break COT control unless you add an RC network to synthesize ripple.
Hysteretic control switches when output voltage hits upper or lower thresholds. Zero phase lag, fastest possible response. The switching frequency varies with input voltage, load, and component tolerance, making EMI filtering difficult.
From field experience, current-mode dominates in applications requiring wide input voltage range (automotive, industrial), COT serves point-of-load converters with tight board space, and voltage-mode persists in low-cost consumer products where 100 kHz bandwidth suffices.
When Simple Feedback Control Fails
Three failure modes appear in production that simulations often miss:
Ceramic capacitor resonance: Multi-layer ceramic capacitors have an ESR zero and ESL pole creating a resonance peak at 1–10 MHz. If this peak falls within the feedback loop bandwidth, the system oscillates. Damping requires adding 0.1–1 Ω series resistance, which defeats the low-ESR advantage. I've debugged designs where the prototype worked fine with tantalum output caps (high ESR, no resonance), then oscillated in production after a cost-reduction switch to ceramics.
Input supply impedance positive feedback: If the buck converter shares a power rail with other circuits, and the input supply has significant impedance at the converter's feedback crossover frequency, the input voltage ripple couples into the control loop. At the right phase angle, this creates positive feedback and oscillation. The classic symptom: converter works on a lab bench supply (low impedance) but oscillates when powered from a USB hub (higher impedance from cable and hub regulation). Adding 100–220 µF bulk capacitance at the converter input decouples it from the supply impedance.
Subharmonic oscillation from PCB layout: Poor ground return paths create inductance in the output capacitor current loop. This inductance resonates with the output capacitance at a frequency near the switching frequency. If the resonance falls at fs/2, every other switching cycle sees different loop gain, and the converter oscillates at fs/2. Oscilloscope shows clean output voltage but 50–100 mV triangular noise at half the switching frequency. The only fix is layout rework to reduce return-path inductance below 100 nH.
Component Selection Constraints
Inductor: Sized by ripple current equation. Also check saturation current (must exceed peak current by 20–30% margin) and DCR (contributes I²R loss). Shielded inductors reduce EMI but cost more. I've seen inductors with identical datasheet specifications behave differently under transient conditions—saturation current ratings are DC values, but pulse saturation occurs earlier due to core heating.
Output capacitor: ESR sets output ripple voltage (Vripple ≈ ΔI × ESR). Capacitance determines hold-up time during load transients. Ceramic offers low ESR but requires parallel bulk capacitance (electrolytic or polymer) for transient energy storage. Electrolytic has high ESR but large capacitance. In practice, most designs use both: ceramic for high-frequency filtering, electrolytic for energy reservoir.
MOSFET: ON-resistance Rds(on) sets conduction loss (I²×Rds(on)). Gate charge Qg sets switching loss (Qg × Vgs × fsw). Low Rds(on) MOSFETs have high Qg, creating a tradeoff: at low switching frequencies (100–200 kHz), optimize for Rds(on); at high frequencies (1 MHz+), optimize for Qg. Synchronous rectification (replacing the freewheeling diode with a second MOSFET) saves 3–5% efficiency but requires dead-time control to prevent shoot-through.
Diode (if not synchronous): Schottky required for efficiency; standard PN diodes have 0.7V forward drop that kills efficiency at low output voltages. Reverse recovery time matters at switching frequencies above 500 kHz—slow diodes cause voltage spikes and ringing.
Application-Based Switching Frequency Selection
| Application | Switching Frequency | Rationale |
|---|---|---|
| Low-cost 5V supply | 300–500 kHz | Minimizes gate drive and switching losses; allows cheaper inductors and MOSFETs |
| Low-noise RF/analog | 1–2 MHz | Pushes switching harmonics above sensitive frequency bands; smaller magnetics reduce board space |
| Battery light-load optimization | 100–300 kHz with pulse-skipping | Lower frequency reduces quiescent current; pulse-skipping enters DCM for high light-load efficiency |
| High-current CPU/GPU | 500 kHz–1 MHz multi-phase | Interleaved phases cancel ripple at input/output; frequency high enough for fast transient response |
PCB Layout as a Hard Constraint
Poor layout destroys an otherwise correct design. The high di/dt current loop (input capacitor → MOSFET → inductor → diode/sync FET → ground → input capacitor) must stay under 1 cm² area. Every millimeter of trace adds inductance (1–2 nH/mm), and at 1 MHz switching with 5A current steps, L×di/dt creates 10–20V voltage spikes.
From my observation, 40% of prototype failures trace to layout issues. Specific rules:
- Input capacitor placement: Must be within 5 mm of MOSFET source/drain pins; farther distances add loop inductance
- Ground return path: Separate high-current power ground from sensitive analog/feedback ground; connect only at one point (star ground)
- Kelvin sense connection: Feedback resistor divider connects directly to output capacitor positive terminal, not to a general PCB trace
- Thermal vias: MOSFET and inductor need thermal relief to internal copper planes; 6–10 thermal vias per component typical
- Layer stack-up: 4-layer boards place ground plane on layer 2, power plane on layer 3, keeping high-current loops on top layer with solid return plane directly underneath
Measurement: Oscilloscope probe ground spring (not clip lead) at MOSFET drain shows switching node ringing. Poor layout: 50–100V overshoot with 20–50 MHz ringing. Optimized layout: <20V overshoot, damped in 2–3 cycles. The difference is inductance—200 nH in poor layout vs 50 nH optimized.
Dead-Time Losses and Synchronous Rectification
In synchronous buck converters, both MOSFETs cannot conduct simultaneously or shoot-through current destroys them. Dead-time (5–20 ns typical) ensures one MOSFET turns off before the other turns on. During dead-time, inductor current flows through the body diode of the low-side MOSFET, dropping 0.7–1.0V instead of the 10–50 mV across Rds(on).
Dead-time loss calculation: At 1 MHz switching with 10 ns dead-time and 5A load current, loss = 5A × 0.8V × 10ns × 1 MHz = 40 mW per amp, or roughly 1% efficiency loss at 5V output. At 500 kHz, same dead-time costs 0.2%. This explains why ultra-high-frequency designs (2–5 MHz for miniaturization) struggle to exceed 90% efficiency—dead-time and switching losses dominate.
The Honest Limitation
No analytical method exists to select all component values correctly on the first pass. Ripple equations and mode boundary formulas guide initial choices, but real inductor saturation behavior under transient conditions, feedback loop phase margin across component tolerance and temperature, and PCB parasitics all require iteration.
Most experienced designers start from a reference design close to the target specification, simulate in SPICE with realistic parasitics models (not ideal components), then build a prototype and validate with oscilloscope measurements of switching node waveforms, output ripple, and load transient response. Datasheet "typical application" circuits work only within narrow operating ranges; scaling voltage, current, or frequency by 2× often requires complete redesign.
Inductor saturation under pulse current is particularly unpredictable—datasheet saturation current is measured with DC, but short pulses (microseconds) can push 20–30% higher before core saturation. Whether this helps or hurts depends on thermal time constants, and batch-to-batch core material variation means some production units saturate earlier than prototypes.
Design Verification Checklist
- Ripple current target: Calculate ΔI for chosen L and fsw; verify inductor saturation current exceeds I_load + ΔI/2 by 30% margin
- CCM margin: Ensure minimum load exceeds I_load,min by 2× to avoid DCM boundary crossing during normal operation
- Output capacitor ESR: Verify ripple voltage ΔI × ESR meets specification; check capacitor voltage rating exceeds Vout by 2× for reliability
- SPICE loop simulation: Confirm phase margin >45° and gain margin >6 dB across input voltage and load range; check step response for overshoot and settling time
- Gate driver timing: Verify dead-time sufficient to prevent shoot-through (measure with current probe on input capacitor—shoot-through appears as narrow current spikes)
- Prototype oscilloscope validation: Measure switching node at MOSFET drain (expect clean trapezoid with <20V overshoot), output ripple (expect triangle wave at fsw), and load transient response (step load 10–90% in <1 µs, measure voltage dip and recovery time)
Conclusion
Buck converter design is a multi-dimensional optimization: efficiency vs size vs cost vs transient response. The duty cycle equation Vout = D×Vin describes steady-state behavior, but production success depends on managing ripple-frequency tradeoffs, preventing CCM-to-DCM boundary crossings under light load, compensating feedback loops for stability across operating range, minimizing dead-time losses, and controlling PCB layout inductance.
Most failures trace to underestimating one constraint: choosing frequency too high and hitting dead-time efficiency floor, sizing inductors for ideal ripple percentage without checking saturation under transients, or assuming feedback loop stability from simulation without validating layout parasitics on prototype hardware.
Oscilloscope validation on prototype PCB before production commit is non-negotiable. Specs lie; real-world testing doesn't.
